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cmos, 5 v/+5 v/+3 v, triple spdt switch adg633 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2009 analog devices, inc. all rights reserved. features 2 v to 6 v dual-supply operation 2 v to 12 v single-supply operation automotive temperature range: ?40c to +125c <0.2 na leakage currents 52 on resistance over full signal range rail-to-rail switching operation 16-lead lfcsp and tssop packages typical power consumption: <0.1 w ttl-/cmos-compatible inputs package upgrades to 74hc4053 and max4053/max4583 applications automotive applications automatic test equipment data acquisition systems battery-powered systems communications systems audio and video signal routing relay replacement sample-and-hold systems industrial control systems functional block diagram s1b d1 s1a s2a d2 s2b s3a d3 s3b a0 a1 a2 en logic adg633 switches shown for a logic 1 input. 0 3275-001 figure 1. general description the adg633 is a low voltage cmos device comprising three independently selectable single-pole, double-throw (spdt) switches. the device is fully specified for 5 v, +5 v, and +3 v supplies. the adg633 switches are turned on with a logic low (or high) on the appropriate control input. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. an en input is used to enable or disable the device. when the device is disabled, all channels are switched off. the adg633 is designed on an enhanced process that provides lower power dissipation, yet is capable of high switching speeds. low power consumption and an operating supply range of 2 v to 12 v make the adg633 ideal for battery-powered, portable instruments. all channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. all digital inputs have 0.8 v to 2.4 v logic thresholds, ensuring ttl/cmos logic compatibility when using single +5 v or dual 5 v supplies. the adg633 is available in a small, 16-lead tssop package and a 16-lead, 4 mm 4 mm lfcsp package. product highlights 1. single- and dual-supply operation. the adg633 offers high performance and is fully specified and guaranteed with 5 v, +5 v, and +3 v supply rails. 2. automotive temperature range: ?40c to +125c. 3. guaranteed break-before-make switching action. 4. low power consumption, typically <0.1 w. 5. small, 16-lead tssop and 16-lead, 4 mm 4 mm lfcsp packages.
adg633 rev. a | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dual-supply operation ............................................................... 3 ? single-supply operation ............................................................. 4 ? absolute maximum ratings ............................................................6 ? esd caution...................................................................................6 ? pin configuration and function descriptions ..............................7 ? typical performance characteristics ..............................................8 ? terminology .................................................................................... 11 ? test circuits ..................................................................................... 12 ? outline dimensions ....................................................................... 14 ? ordering guide .......................................................................... 14 ? revision history 11/09rev. 0 to rev. a changes to table 4 ............................................................................ 6 added table 5; renumbered sequentially .................................... 7 changes to table 6 ............................................................................ 7 update outline dimensions ......................................................... 14 changes to ordering guide .......................................................... 14 2/03revision 0: initial version
adg633 rev. a | page 3 of 16 specifications dual-supply operation v dd = +5 v, v ss = ?5 v, gnd = 0 v, t a = ?40c to +125c, unless otherwise noted. table 1. b version y version parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v ss to v dd v v dd = +4.5 v, v ss = ?4.5 v on resistance, r on 52 typ v s = 4.5 v, i s = 1 ma; see figure 20 75 90 100 max v s = 4.5 v, i s = 1 ma; see figure 20 on-resistance match between channels, r on 0.8 typ v s = +3.5 v, i s = 1 ma 1.3 1.8 2 max v s = +3.5 v, i s = 1 ma on-resistance flatness, r flat(on) 9 typ v dd = +5 v, v ss = ?5 v, v s = 3 v, i s = 1 ma 12 13 14 max v dd = +5 v, v ss = ?5 v, v s = 3 v, i s = 1 ma leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s(off) 0.005 na typ v d = 4.5 v, v s = + 4.5 v; see figure 21 0.2 5 na max v d = 4.5 v, v s = + 4.5 v; see figure 21 drain off leakage, i d(off) 0.005 na typ v d = 4.5 v, v s = + 4.5 v; see figure 22 0.2 5 na max v d = 4.5 v, v s = + 4.5 v; see figure 22 channel on leakage, i d(on) , i s(on) 0.005 na typ v d = v s = 4.5 v; see figure 23 0.2 5 na max v d = v s = 4.5 v; see figure 23 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 1 a max v in = v inl or v inh digital input capacitance, c in 2 pf typ dynamic characteristics 1 t transition 60 ns typ r l = 300 , c l = 35 pf, v s = 3 v; see figure 24 90 110 130 ns max r l = 300 , c l = 35 pf, v s = 3 v; see figure 24 t on ( en ) 70 ns typ r l = 300 , c l = 35 pf, v s = 3 v; see figure 26 95 120 135 ns max r l = 300 , c l = 35 pf, v s = 3 v; see figure 26 t off ( en ) 25 ns typ r l = 300 , c l = 35 pf, v s = 3 v; see figure 26 40 45 50 ns max r l = 300 , c l = 35 pf, v s = 3 v; see figure 26 break-before-make time delay, t bbm 40 ns typ r l = 300 , c l = 35 pf, v s1 = v s2 = 3 v; see figure 25 10 ns min r l = 300 , c l = 35 pf, v s1 = v s2 = 3 v; see figure 25 charge injection 2 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 27 4 pc max v s = 0 v, r s = 0 , c l = 1 nf; see figure 27 off isolation ?90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 total harmonic distortion, thd + n 0.025 % typ r l = 600 , 2 v p-p, f = 20 hz to 20 khz channel-to-channel crosstalk ?90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 30 ?3 db bandwidth 580 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s(off) 4 pf typ f = 1 mhz c d(off) 7 pf typ f = 1 mhz c d(on) , c s(on) 12 pf typ f = 1 mhz power requirements v dd = +5.5 v, v ss = ?5.5 v i dd 0.01 a typ digital inputs = 0 v or 5.5 v 1 a max digital inputs = 0 v or 5.5 v i ss 0.01 a typ digital inputs = 0 v or 5.5 v 1 a max digital inputs = 0 v or 5.5 v 1 guaranteed by design; not subject to production test.
adg633 rev. a | page 4 of 16 single-supply operation v dd = 5 v, v ss = 0 v, gnd = 0 v, t a = ?40c to +125c, unless otherwise noted. table 2. b version y version parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 to v dd v v dd = 4.5 v, v ss = 0 v on resistance, r on 85 typ v s = 0 v to 4.5 v, i s = 1 ma; see figure 20 150 160 200 max v s = 0 v to 4.5 v, i s = 1 ma; see figure 20 on-resistance match between channels, r on 4.5 typ v s = +3.5 v, i s = 1 ma 8 9 10 max v s = +3.5 v, i s = 1 ma on-resistance flatness, r flat(on) 13 14 16 typ v dd = 5 v, v ss = 0 v, v s = 1.5 v to 4 v, i s = 1 ma leakage currents v dd = 5.5 v source off leakage, i s(off) 0.005 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 21 0.2 5 na max v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 21 drain off leakage, i d(off) 0.005 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 22 0.2 5 na max v s = 1 v/4.5 v, v d = 4.5 v/1 v; see figure 22 channel on leakage, i d(on) , i s(on) 0.005 na typ v s = v d = 1 v or 4.5 v; see figure 23 0.2 5 na max v s = v d = 1 v or 4.5 v; see figure 23 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 1 a max v in = v inl or v inh digital input capacitance, c in 2 pf typ dynamic characteristics 1 t transition 100 ns typ r l = 300 , c l = 35 pf, v s = 3 v; see figure 24 150 190 220 ns max r l = 300 , c l = 35 pf, v s = 3 v; see figure 24 t on ( en ) 100 ns typ r l = 300 , c l = 35 pf, v s = 3 v; see figure 26 150 190 220 ns max r l = 300 , c l = 35 pf, v s = 3 v; see figure 26 t off ( en ) 25 ns typ r l = 300 , c l = 35 pf, v s = 3 v; see figure 26 35 45 50 ns max r l = 300 , c l = 35 pf, v s = 3 v; see figure 26 break-before-make time delay, t bbm 90 ns typ r l = 300 , c l = 35 pf, v s1 = v s2 = 3 v; see figure 25 10 ns min r l = 300 , c l = 35 pf, v s1 = v s2 = 3 v; see figure 25 charge injection 0.5 pc typ v s = 2.5 v, r s = 0 , c l = 1 nf; see figure 27 1 pc max v s = 2.5 v, r s = 0 , c l = 1 nf; see figure 27 off isolation ?90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 channel-to-channel crosstalk ?90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 30 ?3 db bandwidth 520 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s(off) 5 pf typ f = 1 mhz c d(off) 8 pf typ f = 1 mhz c d(on) , c s(on) 12 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.01 a typ digital inputs = 0 v or 5.5 v 1 a max digital inputs = 0 v or 5.5 v 1 guaranteed by design; not subject to production test.
adg633 rev. a | page 5 of 16 v dd = 2.7 v to 3.6 v, v ss = 0 v, gnd = 0 v, t a = ?40c to +125c, unless otherwise noted. table 3. b version y version parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 to v dd v v dd = 2.7 v, v ss = 0 v on resistance, r on 185 typ v s = 0 v to 2.7 v, i s = 0.1 ma; see figure 20 300 350 400 max v s = 0 v to 2.7 v, i s = 0.1 ma; see figure 20 on-resistance match between channels, r on 2 typ v s = +1.5 v, i s = 0.1 ma 4.5 6 7 max v s = +1.5 v, i s = 0.1 ma leakage currents v dd = 3.3 v source off leakage, i s(off) 0.005 na typ v s = 1 v/3 v, v d = 3 v/1 v; see figure 21 0.2 5 na max v s = 1 v/3 v, v d = 3 v/1 v; see figure 21 drain off leakage, i d(off) 0.005 na typ v s = 1 v/3 v, v d = 3 v/1 v; see figure 22 0.2 5 na max v s = 1 v/3 v, v d = 3 v/1 v; see figure 22 channel on leakage, i d(on) , i s(on) 0.005 na typ v s = v d = 1 v or 3 v; see figure 23 0.2 5 na max v s = v d = 1 v or 3 v; see figure 23 digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.5 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 1 a max v in = v inl or v inh digital input capacitance, c in 2 pf typ dynamic characteristics 1 t transition 170 ns typ r l = 300 , c l = 35 pf, v s = 1.5 v; see figure 24 300 370 400 ns max r l = 300 , c l = 35 pf, v s = 1.5 v; see figure 24 t on ( en ) 200 ns typ r l = 300 , c l = 35 pf, v s = 1.5 v; see figure 26 310 380 420 ns max r l = 300 , c l = 35 pf, v s = 1.5 v; see figure 26 t off ( en ) 30 ns typ r l = 300 , c l = 35 pf, v s = 1.5 v; see figure 26 40 55 75 ns max r l = 300 , c l = 35 pf, v s = 1.5 v; see figure 26 break-before-make time delay, t bbm 180 ns typ r l = 300 , c l = 35 pf, v s1 = v s2 = 1.5 v; see figure 25 10 ns min r l = 300 , c l = 35 pf, v s1 = v s2 = 1.5 v; see figure 25 charge injection 1 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf; see figure 27 2 pc max v s = 1.5 v, r s = 0 , c l = 1 nf; see figure 27 off isolation ?90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 28 channel-to-channel crosstalk ?90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 30 ?3 db bandwidth 500 mhz typ r l = 50 , c l = 5 pf; see figure 29 c s(off) 5 pf typ f = 1 mhz c d(off) 8 pf typ f = 1 mhz c d(on) , c s(on) 12 pf typ f = 1 mhz power requirements v dd = 3.3 v i dd 0.01 a typ digital inputs = 0 v or 3.3 v 1 a max digital inputs = 0 v or 3.3 v 1 guaranteed by design; not subject to production test.
adg633 rev. a | page 6 of 1 6 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to v ss 13 v v dd to gnd ?0.3 v to +13 v v ss to gnd +0.3 v to ?6.5 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v digital inputs 1 gnd ? 0.3 v to v dd + 0.3 v or 10 ma, whichever occurs first peak current, s or d 40 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s or d 20 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 16-lead tssop 150.4c/w 16-lead lfcsp, 4-layer board 70c/w lead soldering lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 220c (pb-free) soldering reflow, peak temperature 260(+0/?5)c time at peak temperature 20 sec to 40 sec esd 4 kv 1 overvoltages at ax, en , s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution
adg633 rev. a | page 7 of 16 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 s2a s3b d3 v ss en s3a s2b gnd 16 15 14 13 12 11 10 9 d2 d1 s1b a1 a2 a0 s1a v dd adg633 top view (not to scale) 03275-002 figure 2. tssop pin configuration notes 1. the exposed paddle can be left floating or be tied to v dd , v ss , or gnd. pin 1 indicator 1 s3b 2 d3 3 s3a 4 en 11 s1b 12 d1 10 s1a 9a0 5 v ss 6 g nd 7 a2 8 a1 15 s2b 16 s2a 14 v dd 13 d2 adg633 top view (not to scale) 03275-003 figure 3. lfcsp pin configuration table 5. pin function descriptions pin no. mneonic description tssop lfcsp 1 15 s2b source terminal of multiplexer 2. can be an input or output. 2 16 s2a source terminal of multiplexer 2. can be an input or output. 3 1 s3b source terminal of multiple xer 3. can be an input or output. 4 2 d3 drain terminal of multiplexe r 3. can be an input or output. 5 3 s3a source terminal of multiplexer 3. can be an input or output. 6 4 en digital control input. disables all multiplexers when set high. 7 5 v ss most negative power supply terminal. tie this pin to gnd when using the device with single-supply voltages. 8 6 gnd ground (0 v) reference. 9 7 a2 digital control input. 10 8 a1 digital control input. 11 9 a0 digital control input. 12 10 s1a source terminal of multiplexer 1. can be an input or output. 13 11 s1b source terminal of multiplexer 1. can be an input or output. 14 12 d1 drain terminal of multiplexe r 1. can be an input or output. 15 13 d2 drain terminal of multiplexe r 2. can be an input or output. 16 14 v dd most positive power supply terminal. n/a ep ep exposed paddle. the exposed paddle ca n be left floating or be tied to v dd , v ss , or gnd. table 6. adg633 truth table switch condition a2 a1 a0 en switch s1ad1 switch s1bd1 switch s2ad2 switch s2bd2 switch s2ad3 switch s3bd3 x 1 x 1 x 1 1 off off off off off off 0 0 0 0 on off on off on off 0 0 1 0 off on on off on off 0 1 0 0 on off off on on off 0 1 1 0 off on off on on off 1 0 0 0 on off on off off on 1 0 1 0 off on on off off on 1 1 0 0 on off off on off on 1 1 1 0 off on off on off on 1 x = the logic state does not matter; it can be either 0 or 1.
adg633 rev. a | page 8 of 16 typical performance characteristics 100 90 80 70 60 50 40 30 20 10 0 ?5.5 ?3.5 ?1.5 0.5 2.5 4.5 on resistance ( ? ) v d , v s (v) t a = 25c v dd , v ss = 5.5v v dd , v ss = 3.3v v dd , v ss = 5v v dd , v ss = 3v v dd , v ss = 4.5v v dd , v ss = 2.7v 03275-004 figure 4. on resistance vs. v d (v s ), dual supplies 250 200 150 100 50 0 01 10 8 6 4 2 on resistance ( ? ) v d , v s (v) 2 v dd = 2.7v v d d = 3 v v dd = 3.3v v dd = 4.5v v dd = 5v v dd = 5.5v v dd = 10v v dd = 12v t a = 25c 03275-005 figure 5. on resistance vs. v d (v s ), single supply 100 90 80 70 60 50 40 30 20 10 0 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 on resistance ( ? ) v d , v s (v) +125c +85c +25c ?40c v dd = 5v v ss = 5v 03275-006 figure 6. on resistance vs. v d (v s ) for various temperatures, dual supplies 140 120 100 80 60 40 20 0 05 4.54.03.5 3.0 2.52.01.51.00.5 on resistance ( ? ) v d , v s (v) . 0 v dd = 5v v ss = 0v +125c +85c +25c ?40c 03275-007 figure 7. on resistance vs. v d (v s ) for various temperatures, single supply 300 250 200 150 100 50 0 03 2.5 2.0 1.5 1.0 0.5 on resistance ( ? ) v d , v s (v) v dd = 3v v ss = 0v . 0 +125c +85c +25c ?40c 03275-008 figure 8. on resistance vs. v d (v s ) for various temperatures, single supply 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 120 100 80 60 40 20 leakage current (na) temperature (c) v dd = +5v v ss = ?5v v d = 4v v s = 4v i s(off) i d(off) i s(on) , i d(on) 03275-009 figure 9. leakage current vs. temperature, dual supplies
adg633 rev. a | page 9 of 16 i s(off) , i d(off) i s(on) , i d(on) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 120 100 80 60 40 20 leakage current (na) temperature (c) v dd = +5v v ss = 0v v d = 4v v s = 1v v dd = +3v v ss = 0v v d = 2.4v v s = 1v 03275-010 figure 10. leakage current vs. temperature, single supply v dd = +5v v ss = 0v v dd = +3v v ss = 0v v dd = +5v v ss = ?5v 14 ?4 ?2 0 2 4 6 8 10 12 ?5 5 43210 ?1 ?2?3 ?4 q inj (pc) v s (v) t a = 25c 03275-011 figure 11. charge injection vs. source voltage t on t off 100 90 80 70 60 50 40 30 20 10 0 ?40 120 100 80604020 0 ?20 time (ns) temperature (c) v dd = +5v v ss = ?5v 03275-012 figure 12. t on /t off times vs. temperature, dual supplies 300 250 200 150 100 50 0 ?40 120 100 80604020 0 ?20 time (ns) temperature (c) t off v dd = 3v v dd = 3v v dd = 5v v ss = 0v t on 03275-013 figure 13. t on /t off times vs. temperature, single supply 0 ?2 ?4 ?6 ?8 ?10 100k 1m 10m 100m attenuation (db) frequency (hz) v dd = +5v v ss = ?5v t a = 25c 03275-014 figure 14. on response vs. frequency 0 ?20 ?40 ?60 ?80 ?120 ?100 100k 1m 10m 100m off isolation (db) frequency (hz) v dd = +5v v ss = ?5v t a = 25c 03275-015 figure 15. off isol ation vs. frequency
adg633 rev. a | page 10 of 1 6 0 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100k 1m 10m 100m crosstalk (db) frequency (hz) v dd = ?5v v ss = +5v t a = 25c 03275-016 figure 16. crosstalk vs. frequency 100 0.01 0.1 1 10 100 20 1k 10k 20k thd + n (%) frequency (hz) 600? input and output v dd = +5v v ss = ?5v t a = 25c 03275-017 figure 17. thd + noise vs. frequency 10k 1k 100 10 1 0.1 0.01 024681012 i dd (a) v (en) (v) v ss = 0v v dd = 12v v dd = 5v v dd = 3v 03275-018 figure 18. v dd current vs. logic level 3.0 2.5 2.0 1.5 1.0 0.5 0 024681012 logic threshold voltage (v) v dd (v) 03275-019 figure 19. logic threshold voltage vs. v dd
adg633 rev. a | page 11 of 1 6 terminology v dd most positive power supply potential. v ss most negative power supply potential. i dd positive supply current. i ss negative supply current. gnd ground (0 v) reference. s source terminal. can be an input or output. d drain terminal. can be an input or output. a x logic control input. en active low digital input. when en is high, the device is disabled and all switches are off. when en is low, the ax logic inputs determine the on switches. v d , v s analog voltage on terminal d and terminal s. r on ohmic resistance between terminal d and terminal s. r on on-resistance match between any two channels, that is, r onmax ? r onmin . r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. i s(off) source leakage current with the switch off. i d(off) drain leakage current with the switch off. i d(on) , i s(on) channel leakage current with the switch on. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl , i inh input current of the digital input. c s(off) off switch source capacitance. measured with reference to ground. c d(off) off switch drain capacitance. measured with reference to ground. c d(on) , c s(on) on switch capacitance. measured with reference to ground. c in digital input capacitance. t on ( en ) delay between applying the digital control input and the output switching on (see figure 26 ). t off ( en ) delay between applying the digital control input and the output switching off (see figure 26 ). t bbm on time, measured between 80% points of both switches when switching from one address state to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch.
adg633 rev. a | page 12 of 1 6 test circuits i ds v1 sd v s r on = v1/i ds 0 3275-020 figure 20. on resistance sd v s v d i s(off) i d(off) a a 03275-021 figure 21. source off leakage sd v d i d(on) a nc nc = no connect 03275-022 figure 22. drain off leakage s1a d v s v d s1b gnd en a i d(on) v dd v ss v dd v ss 03275-023 figure 23. channel on leakage en 90% 90% 50% 50% v out address drive (v in ) t transition t transition 3v 0v v dd v ss v s1a v out v in a2 a1 a0 gnd s1a s1b d adg633 v dd v ss 50? r l 300? 0.1f 0.1f c l 35pf v s1b 03275-024 figure 24. transition time, t transition en t bbm 3v address drive (v in ) v out 0v v dd v ss v s v out v in a2 a1 a0 gnd s1a s1b d1 adg633 80% 80% v dd v ss 50 ? r l 300? c l 35pf 0.1f 0.1f 03275-025 figure 25. break-before-make delay, t bbm
adg633 rev. a | page 13 of 1 6 en 0.1f 0.1f v s v out 50? a2 a1 a0 gnd s1a s1b d1 v in adg633 r l 300? c l 35pf v ss v dd v ss v dd 0.9v out 50% 50% 3v 0v v out 0v enable drive (vin) output 0.9v out t off (en) t on (en) 03275-026 figure 26. enable delay, t on ( en ), t off ( en ) a2 a1 a0 gnd d adg633 s v out v dd v ss v dd v ss v s v in r s c l 1nf en 3v 0v v out logic input (v in ) q inj = c l v out v out 0 3275-027 figure 27. charge injection v dd v ss v dd v ss en a2 a1 a0 gnd s d 50? v out v s logic 1 0.1f 0.1f network analyzer 50 ? r l 50? off isolation = 20 log v out v s 03275-028 figure 28. off isolation v dd v ss v dd v ss en a2 a1 a0 gnd s d insertion loss = 20 log v out with switch v out without switch r l 50? v out 50 ? v s 0.1f 0.1f network analyzer 0 3275-029 figure 29. bandwidth en a2 a1 a0 gnd sa da 0.1f v out db 50 ? v s adg633 crosstalk = 20 log v out v s 0.1f r l 50 ? network analyzer network analyzer 50 ? v dd v ss v dd v ss 03275-030 figure 30. channel-to-channel crosstalk
adg633 rev. a | page 14 of 1 6 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 31. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters compliant to jedec standards mo-220-vggc 2 . 2 5 2 . 1 0 s q 1 . 9 5 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indicator top view 4.00 bsc sq 3.75 bsc sq coplanarity 0.08 (bottom view) 12 max 1.00 0.85 0.80 seating plane 0.35 0.30 0.25 0.80 max 0.65 typ 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indicator 0.25 min 072808-a 0.75 0.60 0.50 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 32. 16-lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-4) dimensions shown in millimeters ordering guide model temperature range package description package option adg633yru ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 adg633yru-reel7 ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 adg633yruz 1 ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 adg633yruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package (tssop) ru-16 adg633ycp ?40c to +85c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-4 ADG633YCP-REEL7 ?40c to +85c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-4 adg633ycpz 1 ?40c to +85c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-4 adg633ycpz-reel7 1 ?40c to +85c 16-lead lead frame chip scale package (lfcsp_vq) cp-16-4 1 z = rohs compliant part.
adg633 rev. a | page 15 of 1 6 notes
adg633 rev. a | page 16 of 16 notes ?2003C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03275-0-11/09(a)

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